1. Field of the Invention
The present invention relates to generation of intentional time delays into incoming signals.
2. Description of the Related Art
A conventional time delay system in shown in FIG. 1a. The time delay system 40 includes a series/parallel combination of buffers 12, 16, 18, 22, 24, 26, 28, 32 through 34 and multiplexers 14, 20, 30, and 36. The time delay system 40 also includes delay control bits S0-S3. Each of the buffers 12, 16, 18, 22, 24, 26, 28, 32 through 34 is a delay element that provides a time delay into its input signal. The delay control bits S0-S3 control multiplexers 14, 20, 30, and 36 so that the multiplexers select either signals or non-delayed signals. For instance if S0 is 0, then the multiplexer 14 chooses the non-delayed input signal at a node 10 rather than the input-signal delayed by the time delayed associated with the buffer 12. In operation, if the delay control bits S0-S3 are 1100, then the output signal 38 is the input signal 10 delayed by the time delay of the buffers 12, 16, and 18 and the intrinsic time delay associated with the multiplexers 14, 20, 30, and 36.
Another known approach is illustrated conceptually in FIG. 14a. This scheme provides the same functionality as the approach in FIG. 1, but it eliminates the concatenation of multiple multiplexers. A third known approach shown in FIG. 14b is to use a resistive ladder to delay the incoming signal based on an RC time constant. As the values of resistors 1041, 1043, 1045 and 1047 are increased by linear multiples of some value R, and the value C is the same for capacitors 1048, the delay step .tau..sub.delta produced by the ladder equals .tau..sub.RC.
The two approaches of FIGS. 14a and 14b can be combined such that the output 1044 of the time delay system of FIG. 14a is coupled to the input node 1049 of the time-delay system of FIG. 14b, wherein the time delay system of FIG. 14a acts as a coarse vernier and the time delay system of FIG. 14b acts as a fine adjustment.
Another well-known technique is illustrated in FIG. 15a, wherein a voltage 1054 through resistor R is connected to an integrator formed by capacitor 1056 and amplifier 1058 at a known time t corresponding to the rising edge of an input signal to be delayed. The voltage at the output of the integrator is a ramping voltage which is quite linear and which has a duration equal to the delay range of the circuit. The ramp voltage is input to one input of a comparator circuit 1060. The other input of comparator 1060 is coupled to the output of a digital-to-analog converter (DAC) 1062. The DAC 1062 produces a voltage which is linearly proportional to the n-bit digital program work presented on DAC input 1064.
When the ramp voltage hits the same voltage level as that which is output by the DAC 1062, the comparator switches and produces an edge which is delayed by the amount of time it took for the ramp to reach the DAC voltage level.
One application of the conventional time delay system or the present invention is in generating deskew delays for a random access memory (RAM) tester as shown in FIG. 1b. A timing generator 46 provides test signals to the test devices such as RAM 1, RAM 2, and RAM N. The test devices RAMs 1-N are connected to the timing generator 46 through cables 1-N. Because the cables 1-N are different in length, the signals sent by the timing generator 46 arrive at the test devices RAMs 1-N at difference times. In order to have the signals arrive at the test devices RAMs 1-N at the same time, deskew delay units 1-N may be provided as shown in FIG. 1b. Each of the deskew delay units 1-N may incorporate the time delay system 40 or the present invention which is programmed to provide a time delay so that all of the test devices RAMs 1-N receive the signals from the timing generator 46 at the same time.
One problem associated with the conventional time delay systems is the data dependency error. A data dependency error is described with reference to FIG. 2. A time delay system 51 in FIG. 2 consists of four delay elements including buffers 52, 54, 56, and 58. An input signal 50a at an input node 50 has a repetition period of T.sub.p. A first pulse 50b of the input signal 50a travels through the buffers 52, 54, 56, and 58, and reaches an output node 60 after a time delay Td1. A second pulse 50c of the input signal 50a reaches the output 60 after a time delay of Td2. A data dependency error is defined as Td2-Td1. Ideally, Td1 should be equal to Td2. In such a case, the data dependency error is zero. Typically, a data dependency error is not zero. As the repetition rate T.sub.p decreases, the substrate settling time increases, the data dependency error becomes worse. The substrate settling time will be described in more detail with reference to FIG. 8. In addition, as the required time delay becomes longer, the data dependency error of a delayed signal of a conventional time delay system increases. For example, to provide a long time delay, the time delay system 40 requires more buffers. As more buffers are added, the data dependency error also increases. At some point, the data dependency error may become too large to be acceptable especially for highly accurate timing systems.
Accordingly, there is a need for a time delay system that can provide a minimum data dependency error that is independent of the repetition rate of the input signal, the substrate settling time, and the length of the time delay.